Delay elements arc used in a wide variety of digital timing circuits including ring oscillators, voltage-controlled oscillators, tapped delay lines, and clock buffers. These circuits are in turn used to provide timing signals to data communication circuits, microprocessors, and other digital systems. Depending on the application, delay elements may either have a fixed delay or a variable delay. The delay of a variable delay element is controlled by an input signal that may be either analog or digital. A good delay element is one that dissipates little power and has a very stable delay, exhibiting very low cycle-to-cycle delay variation or jitter in the presence of powersupply noise.
In the prior art, delay elements have been constructed from CMOS inverters, current-starved inverters, and source-coupled FET logic circuits. Such prior-art delay elements are described in Dally and Poulton, Digital Systems Engineering, Cambridge, 1998, pp. 589-603. FIG. 1 shows a prior art tapped delay line formed from a series of CMOS inverters 30. The input signal on the left is delayed to generated signals p1-p4 on the outputs of each inverter. By itself, this line provides a fixed delay. With the addition of a multiplexer to select one of the taps for output, it can provide a discrete variable delay. While CMOS inverter delay lines are simple, their delay is not well controlled. The delay varies with process, voltage, and temperature variations. Cycle-to-cycle variations in the supply voltage result in large cycle-to-cycle delay variations or jitter.
The current-starved delay element of FIG. 2 is an example of a prior-art voltage-controlled delay element. The input signal, in, is delayed by three inverters 32 to generate output, out. Each inverter has its supply and ground current limited by FETs 34 and 36 respectively, wired as current sources. The current, and hence the delay of the line is controlled by control voltage, vctrl. As vctrl is increased the current in each current source is increased allowing the inverters to switch more rapidly and hence reducing delay. The current-starved inverter delay line can be adjusted, by varying vctrl, to compensate for process, temperature, and average supply voltage variations. However, it still has high jitter because of its sensitivity to cycle-to-cycle power supply variations. Also, even with maximum voltage on vctri, its speed is limited by the series connection of the current-source FETs with the inverters. This circuit is discussed in more detail in Dally and Poulton, pp. 211-212 and p. 590.
Most high-performance timing circuits built today use the source-coupled circuit shown in FIG. 3. A differential input, inP, inN, is delayed by three differential source-coupled stages 42 with PFET loads to generate differential output, outP, outN. This circuit has lower jitter than the CMOS inverter or current-starved inverter delay lines because its differential design rejects a portion of the power supply noise. However it dissipates considerably more power than the inverter-based delay lines and still has substantial jitter. Its power supply rejection is not perfect because the current source has a finite output impedance and the load resistors are non-linear. This circuit is described in more detail in Dally and Poulton, pp. 593-603.
Regulating the supply voltage as shown in FIG. 4 can reduce the jitter problem with CMOS inverter delay lines. Input voltage vctrl, through a voltage follower 50, controls the supply voltage to a series of CMOS inverters 52. Regulating the supply voltage with the voltage follower reduces power supply jitter, while the vctrl input allows voltage control over the delay of the line which may be used to adjust for fixed delay variations. This approach is described in more detail in Daily and Poulton, p. 593.
One can also regulate the current to the delay line as shown in FIG. 5. The control voltage, vctrl, generates a current that is mirrored using a cascoded current mirror circuit 60 to supply a constant current to the inverters 62 of a three-element inverter delay line. This approach is described in von Kaenel, "A Low-Power Clock Generator for a Microproccssor Application," Journal of Solid-State Circuits, 33(11), pp. 1634-9.